Fdc / fdd communication doc

[andrew]

Hi Jeff!

I am trying to understand, how fdc / fdd communication works, and it seems not a well documented thing. I found only intel 82077AA doc on internet (fdc lsi on old pc motherboard), nothing else, and realize it lacks signal wave form and timing diagrams of read / write data lines. Also other control signals are not exactly documented.

As i see, you have done a huge job with floppy simulator. Where found you documentation for it?

Thank you for any tipp.

[Jeff]

Hi Jeff!

I am trying to understand, how fdc / fdd communication works, and it seems not a well documented thing. I found only intel 82077AA doc on internet (fdc lsi on old pc motherboard), nothing else, and realize it lacks signal wave form and timing diagrams of read / write data lines. Also other control signals are not exactly documented.

As i see, you have done a huge job with floppy simulator. Where found you documentation for it?

Thank you for any tipp.

Have a look to any FDC datasheet / FDD datasheet. Search also for "floppy.pdf" under google.

[andrew]

There is only one thing i not found exactly: how write operation works?

It says in 82077AA doc, controller starts to read the track on floppy, and after it found sector header, it turns on write gate, and injects write data. While this method on IBM PC (3.5" 1.44 MB 500 kbit/sec MFM encoding), only 1 uSec time difference with that data output pulse makes output bits not "00" but "01" on reading back. Since floppy disc is a mechanical thing, it is always imperfect. And all this will be along a floppy cable fully with parasite loading.

Does it really? I feel it as something unclear, or at least tricky. Could you help me to understand this?

[Jeff]

There is only one thing i not found exactly: how write operation works?

It says in 82077AA doc, controller starts to read the track on floppy, and after it found sector header, it turns on write gate, and injects write data. While this method on IBM PC (3.5" 1.44 MB 500 kbit/sec MFM encoding), only 1 uSec time difference with that data output pulse makes output bits not "00" but "01" on reading back. Since floppy disc is a mechanical thing, it is always imperfect. And all this will be along a floppy cable fully with parasite loading.

Does it really? I feel it as something unclear, or at least tricky. Could you help me to understand this?

Yes it is ! But there are an VFO/PLL circuit between the FDC and the FDD. This help a lot and allow an +/- 15% speed variation. The sync parts on the floppy is to synchronize the VFO / PLL.

[andrew]

Thx tipp, already understand some reference in 82077aa doc too.

However there is something i not found: a simple floppy seek in a practical case.

For example: floppy drive writing sectors when user aggressively pushes the button on front of floppy drive and cuts off the floppy disk.

Which side have to maintain the floppy seek back to track 00? Floppy drive will do it automatically (also reports on track00 line), or the controller side will assert step line as many times as need to parking floppy head back to track 00?

[Jeff]

Thx tipp, already understand some reference in 82077aa doc too.

However there is something i not found: a simple floppy seek in a practical case.

For example: floppy drive writing sectors when user aggressively pushes the button on front of floppy drive and cuts off the floppy disk.

Which side have to maintain the floppy seek back to track 00? Floppy drive will do it automatically (also reports on track00 line), or the controller side will assert step line as many times as need to parking floppy head back to track 00?

this one :

the controller side will assert step line as many times as need to parking floppy head back to track 00.